IGBT power devices and MOS devices find wide and specific application in fields with high voltage and current such as for example in the field of the control circuits and of power switches.
These power devices are generally expected to provide good performances at high switch speeds. The characteristic, fundamental parameters for reducing the switch times in these devices are a low gate charge Qg, and thus a lower gate capacity, and a reduced and uniform gate resistance Rg.
The market is also driving a continuous miniaturization of these power devices.
The power devices, IGBT and MOS, integrated on a semiconductor substrate, comprise a plurality of elemental cells, each having its own gate region, interposed between source and body regions.
The elemental cells are substantially realized in two versions: one with planar gate and the other with trench-gate structure.
In a method for realizing a power device with trench-gate structure, and in particular with a trench of the Metal Insulator Semiconductor (MIS) type, for each elemental cell the gate is realized by means of the formation of a trench, on the semiconductor substrate, whose side walls and whose bottom are covered by an oxide layer, the trench being subsequently filled with a polysilicon layer.
These power devices with trench-gate structure of the MIS type have several advantages in particular they allow an increase in the integration scale with subsequent increase of the current density, as well as an abatement of the JFET resistance, with a substantial improvement of the characteristic in conduction of the device.
However, the power devices with trench-gate structure of the MIS type have some drawbacks. In fact, due to the curved profile of the basal region of the trench, in this region there is a thickening of the electric field, which may overcome the limit of the oxide (e.g., 10 MV/cm) and compromise the insulation between the semiconductor substrate and the upper polysilicon layer. There is a solution to this drawback, which makes the bottom of the trench by suitably sizing the curvature radius of the basal region with a “U”-like profile to reduce or minimize the effects of the thickening of the electric field.
These devices with trench-gate structure have another drawback with respect to the devices with planar gate. In fact, for each elemental cell of these devices, the gate oxide occupies a greater area and this implies an increase of the parasite capacities linked to the gate terminal of the device as a whole.
A known solution realizes the gate electrode in correspondence with the vertical walls of the trench-gate structure, for example as described in FIG. 1 of U.S. Pat. No. 7,205,607, which is incorporated by reference.
Another known solution provides a thickening of the gate oxide in the bottom of the trench and in the walls below the body region, for example as described in FIG. 2 of U.S. Patent application 2007/0063272 which is incorporated by reference.
A similar solution is also described in FIG. 3 of U.S. Pat. No. 7,005,351 which is incorporated by reference, relative to a method for manufacturing a transistor configuration comprising at least one trench transistor cell. Also this solution provides a thick oxide in the bottom of the trench and a thin gate oxide only in the side walls of the trench.
A similar solution is described in FIG. 4 of U.S. Pat. No. 6,528,355, which is incorporate by reference.
According to these solutions, the thick oxide layers, present in correspondence with the bottom of the trench-gate structure, are obtained by means of particular process steps, which employ suitable additional layers overlapped onto the thick oxide layer. The additional layers, of materials such as resist or nitride, are subsequently subjected to etching processes to be removed. These etching processes may, however, compromise the “strength” of the thick oxide and thus the performances of the device obtained, and, in the meantime, increase the number of process steps and the realization times.
Alternatively, these thick oxide layers may be often obtained by means of a selective oxidation step in correspondence with the bottom of the trench. However, this step may crystallographically damage the semiconductor substrate below the bottom of the trench-gate structure, which consequently may reduce the performance of the device thus obtained.